HAL ICACHE initialization and configuration functions migration

The goal of this page is to show how to migrate the initialization sequence using STM32CubeMX2:

  • Open STM32CubeMX2 ICACHE configuration panel.

  • Configure the SW layer HAL.

  • Configure the additional ICACHE features if needed.

  • Configure the NVIC if the application requires the ICACHE to be used in IT mode.

  • Generate the code.

HAL ICACHE configuration panel

Create a new project with the STM32CubeMX2, then start the initialization and the main configuration.

Project configuration panel

HAL ICACHE main features configuration

Configure the ICACHE main features.

ICACHE main feature configuration

HAL ICACHE advanced features configuration

Configure the advanced ICACHE features if needed.

ICACHE advanced feature configuration

NVIC configuration

Configure the NVIC in case of an interrupt.

ICACHE NVIC configuration

Generated ICACHE initialization and de-initialization sequences

The ICACHE initialization and de-initialization sequences are generated in the mx_icache_hal_init function in mx_icache.c file under $YOUR_PROJECT_NAME$/$YOUR_PROJECT_NAME$_SW/generated/STM32Cube_CodeGen.

Related concepts:

STM32CubeMX2 Generated with user values

Topic

HAL1 code snippet

HAL2 code snippet

ICACHE init and config sequences 

static void MX_ICACHE_Init(void)
{






  ICACHE_RegionConfigTypeDef pRegionConfig = {0};

  /** Configure and enable region 0 for memory remapping */
  pRegionConfig.BaseAddress = 0x10000000;
  pRegionConfig.RemapAddress = 0x60000000;
  pRegionConfig.Size = ICACHE_REGIONSIZE_2MB;
  pRegionConfig.TrafficRoute = ICACHE_MASTER1_PORT;
  pRegionConfig.OutputBurstType = ICACHE_OUTPUT_BURST_WRAP;
  if (HAL_ICACHE_EnableRemapRegion(ICACHE_REGION_0, &pRegionConfig) != HAL_OK)
  {
    Error_Handler();
  }

  /** Enable instruction cache (default 2-ways set associative cache) */
  if (HAL_ICACHE_Enable() != HAL_OK)
  {
    Error_Handler();
  }

}

void HAL_MspInit(void)
{

  __HAL_RCC_PWR_CLK_ENABLE();

  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_3);

  /* ICACHE_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(ICACHE_IRQn, 0, 0);
  HAL_NVIC_EnableIRQ(ICACHE_IRQn);

}

hal_icache_handle_t *mx_icache_init(void)
{
  if (HAL_ICACHE_Init(&hICACHE, HAL_ICACHE) != HAL_OK)
  {
    return NULL;
  }

  /* Associativity mode set to default value 2-ways */

  hal_icache_region_config_t p_region_config = {0};

  p_region_config.size          = HAL_ICACHE_REGION_SIZE_2MBYTES;
  p_region_config.base_address  = 0x10000000;
  p_region_config.remap_address = 0x60000000;
  p_region_config.master_port   = HAL_ICACHE_MASTER1_PORT;
  p_region_config.output_burst  = HAL_ICACHE_BURST_WRAP;

  if (HAL_ICACHE_SetConfigRemapRegion(&hICACHE, HAL_ICACHE_REGION_0, &p_region_config) != HAL_OK)
  {
    return NULL;
  }

  if (HAL_ICACHE_EnableRemapRegion(&hICACHE, HAL_ICACHE_REGION_0) != HAL_OK)
  {
    return NULL;
  }

  /* Enable the interruption for ICACHE */
  HAL_CORTEX_NVIC_SetPriority(ICACHE_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
  HAL_CORTEX_NVIC_EnableIRQ(ICACHE_IRQn);

  return &hICACHE;
}











  /* Enable the interruption for ICACHE */
  HAL_CORTEX_NVIC_SetPriority(ICACHE_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
  HAL_CORTEX_NVIC_EnableIRQ(ICACHE_IRQn);

  return &hICACHE;
}

ICACHE deinit sequences 

static void icache_deinit(void)
{
 if (HAL_ICACHE_DeInit() != HAL_OK)
 {
   Error_Handler();
 }
}

void mx_icache_deinit(void)
{
  (void)HAL_ICACHE_DeInit(&hICACHE);

  HAL_CORTEX_NVIC_DisableIRQ(ICACHE_IRQn);
}

ICACHE IRQ handler sequences 

void ICACHE_IRQHandler(void)
{
  HAL_ICACHE_IRQHandler();
}

void ICACHE_IRQHandler(void)
{
  HAL_ICACHE_IRQHandler(&hICACHE);
}